The present disclosure relates to split gate memory cells used in FLASH EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to an architecture to reduce the cell size for compact array of split gate flash memory cell.
Flash cells are used in a wide variety of commercial and military electronic devices and equipment. In flash memory cells, over erase associated with stacked gate structures is eliminated by the use of a split gate structure. However, such structures and the use of dedicated select and erase gate structures adds to the cell size.